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Design Guidelines for TERIDIAN 78P235x LIUs
The DLLs use 32 phase taps to recover a 311MHz clock (nominal phase tap spacing is 100ps). With jitter of the
incoming data and variable transition density, the recovered clock will naturally hop between a couple of taps
even when phase locked. In plesiochronous timing mode, this will appear as high frequency phase jumps or
phase jitter during isolated CMI pulse mask measurements (most noticeable with CMI binary 0) This jitter
generation is normal and inherent to all CDR’s, although more linear with analog PLLs. The magnitude of the
output jitter is directly related to the bandwidth of the Tx CDR which is 80kHz in the case of the 78P235x transmit
CDR. It should be noted this jitter will not effect intrinsic jitter measurements when measured with standards
filters enabled.
The two plots above show a close-in view of the peak-to-peak transmit phase jitter in plesiochronous (left) and
synchronous modes (right). This is most noticeable on the falling edge of a CMI Binary 0 Pulse Template
Measurement. It should be noted that every isolated pulse is still compliant to the Pulse Template requirements,
but mask counting and infinite persistence results will vary from scope to scope depending on acquisition
methods.
Be sure to center triggering position or amplitudes to avoid
false failures on falling edge of CMI - Binary 0 pulse masks
Page 15 of 15
? 2008 Teridian Semiconductor Corp.
Rev 2.1
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相关PDF资料
79-WHITE-1"X60YD
TAPE GLASS CLOTH 1"X 60YD WHT
79059-2701
CONN RECEPT R/A 50POS 4-40 SCSI
79059-2702
CONN RECEPT R/A 68POS 4-40 SCSI
79059-2726
CONN RECEPT R/A 50POS 2-56 SCSI
79278
TAPE CLR ESD YEL STRIPE 2"X72YDS
796014-2
CONN CHAMP GUIDE PIN .050
796055-2
CONN RCPT 68POS .8MM R/A
796068-1
CONN RCPT 40POS .050 VERT
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